The invention lies in the semiconductor and memory technology fields. More specifically, the invention pertains to a method for manufacturing a trench capacitor that can be a component of a memory cell of a semiconductor memory.
Semiconductor memories, such as for example DRAMs (Dynamic Random Access Memories), are made up of a cell field and peripheral drive control equipment. Individual memory cells are situated in the cell field.
A DRAM chip contains a matrix of memory cells that are arranged in the form of rows and columns, and are controlled by word lines and bit lines. The reading out of data from the memory cells, or the writing of data to the memory cells, is accomplished through the activation of suitable word lines and bit lines.
Conventionally, a memory cell of a DRAM contains a transistor that is connected with a capacitor. Among other things, the transistor is made up of two diffusion regions that are separated from one another by a channel that is controlled by a gate. One diffusion region is called the drain region, and the other diffusion region is called the source region.
One of the diffusion regions is connected with a bit line, the other diffusion region is connected with a capacitor, and the gate is connected with a word line. Through application of suitable voltages to the gate, the transistor is controlled in such a way that a flow of current between the diffusion regions through the channel is switched on and switched off.
Due to the progressive miniaturization of memory components, the integration density is continually being increased. The continual increasing of the integration density means that the surface available per memory cell is constantly decreasing. This has the result that the selection transistor and the storage capacitor of a memory cell are subjected to a constant reduction in their geometrical dimensions.
The continuing effort towards miniaturization of memory devices promotes the design of DRAMs having greater density and smaller characteristic size, i.e., smaller memory cell surface. In order to manufacture memory cells that require a smaller surface area, smaller components, such as for example capacitors, are used. However, the use of smaller capacitors results in a lower storage capacity of the individual capacitor, which in turn can have an adverse effect on the functional capability and applicability of the memory device. For example, read amplifiers require a sufficient signal level for the reliable reading out of the information stored in the memory cells. The ratio of storage capacity to bit line capacity is decisive in the determination of the signal level. If the storage capacity becomes too small, this ratio can be too small to produce a sufficient signal for the controlling of the read amplifier. Likewise, a smaller storage capacity requires a higher refresh frequency. An additional disadvantage of a capacitor that has been reduced in its geometrical dimensions is to be found in the electrical supply lines, which are likewise fashioned with a reduced cross-section, through which the resistance of the supply lines is increased and the speed of the individual memory cell is reduced.
According to U.S. Pat. No. 5,744,386 it is known to produce a selective epitaxial layer on an exposed lateral wall in trench capacitors for the formation of a vertical selection transistor.
According to U.S. Pat. No. 6,066,527, it is known, for example, to produce an insulating collar in an upper region of a trench.
It is accordingly an object of the invention to provide a method of fabricating a trench capacitor of a memory cell of a semiconductor memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for lower manufacturing costs and increased capacitance of the trench capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of manufacturing a trench capacitor, which comprises the following method steps:
providing a substrate with a substrate surface;
forming a trench with an upper region, a lower region, and a side wall in the substrate, the upper region being closer to the substrate surface than the lower region;
isotropically etching the trench to widen the trench in the upper region and the lower region;
conformally depositing a first insulating layer in the trench;
etching the first insulating layer with directed etching to form the first insulating layer as a lateral edge web;
removing the first insulating layer from the lower region of the trench, thereby forming an insulating collar in the upper region from the first insulating layer, the collar extending into the trench from the substrate surface down to a first sinking depth;
forming a capacitor dielectric on the substrate in the lower region of the trench and on the insulating collar in the upper region of the trench;
filling the trench with a conductive trench filling;
sinking the insulating collar into the trench down to a second sinking depth located between the substrate surface and the first sinking depth, and exposing the substrate on the side wall of the trench, above the second sinking depth;
sinking the conductive trench filling and the capacitor dielectric into the trench down to a third sinking depth located between the first sinking depth and the second sinking depth;
selective-epitaxially growing a selective epitaxial layer on the exposed side wall of the trench; and
forming an electrical contact between the conductive trench filling and a doping region of a selection transistor. With the novel process there is formed a trench capacitor having a buried insulating collar and an epitaxial layer is formed, which is grown above the insulating collar in the trench, starting at the substrate. The buried insulating collar has the advantage that the trench capacitor is formed with a larger diameter than is provided by the lithographic mask used for its structuring. In this way, the trench capacitor is formed with a larger cross-sectional surface, which on the one hand enables a larger surface of the electrodes of the trench capacitor, through which the capacitance of the trench capacitor is increased, and on the other hand enables a larger cross-sectional surface for the conductive trench filling that forms the inner capacitor electrode of the trench capacitor and forms an electrical connection between the inner capacitor electrode B through the insulating sleeve formed by the insulating collar B to a doping region of a selection transistor. Through the enlarged cross-sectional surface of the conductive trench filling in the tubular insulating jacket formed by the insulating collar, a reduced electrical resistance is enabled, through which the time required for reading out and for storing an item of information in the trench capacitor can be reduced. The inventive combination of the buried insulating collar with a selective epitaxial layer grown above the insulating collar in the trench makes it possible to form the selection transistor of the memory cell closer to the trench capacitor, thus reducing the overall surface claimed by the memory cell. In this way, leakage currents between adjacent contact regions are likewise reduced.
An advantageous construction of the inventive method provides that a masking layer is situated on the substrate surface, and the directed etching of the first insulating layer is carried out selectively to the masking layer with etching gas containing carbon fluoride, such as C4F8, C5F8, or C2F6. Through the described etching with the named etching gases, the first insulating layer is formed in the trench as a lateral edge web. Because a widening of the trench was previously carried out, the masking layer blocks or screens the side wall of the trench, so that the insulating layer remains on the side wall of the trench during the directed etching.
A further construction of the inventive method provides that with the first insulating layer an oxidation step is carried out, at a temperature between 900xc2x0 C. and 1050xc2x0 C., for a duration between 20 and 90 minutes, in an atmosphere containing oxygen and/or nitrogen, in order to seal the first insulating layer.
This method step is suitable for the sealing of an insulating layer deposited by means of a CVD (Chemical vapor Deposition) or LPCVD (Low Pressure CVD) process, through which leakage currents through the insulating layer and at its boundary surface are reduced.
A further method step provides that an etching mask is formed in the upper region of the trench on the insulating layer, said mask being used as an etching mask in the removal of the insulating layer from the lower region of the trench. The etching mask is formed in the upper region of the trench in order to cover the first insulating layer there during an etching, and to protect it from the etching substance. During the etching, the first insulating layer is then removed from the lower region of the trench, while it remains in the upper region of the trench. In this way, the insulating collar is structured out of the first insulating layer and is formed in the upper region of the trench.
A further method step provides that in the trench, a first trench filling is deposited on the first insulating layer and is sunk into the trench up to a first sinking depth, whereby the first trench filling is removed from the upper region of the trench, and a conformal masking layer is deposited in the upper region of the trench on the first insulating layer and on the first trench filling, and is isotropically etched back, whereby lateral edge webs are formed on the first insulating layer that are used as an etching mask for the removal of the first insulating layer from the lower region of the trench. This method at first forms a first trench filling that is sunk into the trench up to a first sinking depth. Above the first trench filling, a masking layer is applied in conformal fashion on the first insulating layer and on the trench filling. The masking layer is subsequently etched with a directed etching step, through which the masking layer is formed as a lateral edge web (spacer) on the first insulating layer, above the first trench filling. The lateral edge webs are now subsequently used as an etching mask in order to protect the first insulating layer in the upper region of the trench, while the first insulating layer is removed from the lower region of the trench.
A further method step provides that in the trench a masking layer is deposited in conformal fashion on the first insulating layer and in the trench, a first trench filling is brought in on the masking layer and is sunk into the trench up to a first sinking depth, whereby the first trench filling is removed from the upper region of the trench, and the masking layer situated above the first sinking depth on the first insulating layer is converted into a modified masking layer through the bringing in of dopant on its surface, and the first trench filling is removed selectively to the modified masking layer from the lower region of the trench, and the masking layer is removed selectively to the modified masking layer from the lower region of the trench, and the modified masking layer is used as an etching mask for the removal of the first insulating layer from the lower region of the trench. This is a further method variant, involving the formation of an etching mask in the upper region of the trench on the first insulating layer, so that the first insulating layer can be removed from the lower region of the trench, while it remains in the upper region of the trench. For this purpose, first a conformal masking layer is deposited in the upper region and in the lower region of the trench on the first insulating layer. Subsequently, the first trench filling is filled in the trench and is sunk into the trench up to the first sinking depth. Here, the masking layer in the lower region of the trench is covered by the first trench filling, and is exposed in the upper region of the trench above the first sinking depth. Subsequently, the masking layer is converted through the bringing in of dopant at its surface. As a p-dopant, for example boron, indium, or gallium can be used, and as an n-dopant phosphorus, arsenic, and antimony are suitable, as well as oxygen or nitrogen.
Subsequently, the first trench filling is removed selectively to the modified masking layer from the lower region of the trench. Because the masking layer in the lower region of the trench has a different doping than does the modified masking layer in the upper region of the trench, the masking layer can likewise be removed selectively to the modified masking layer from the lower region of the trench. Subsequently, the modified masking layer acts as an etching mask in the removal of the first insulating layer from the lower region of the trench.
If, for example, an amorphous silicon layer is used as a masking layer, this layer can be doped with boron by means of a plasma doping. Subsequently, the first trench filling, made up for example of photoresist, is removed from the lower region of the trench. Subsequently, the removal of the masking layer can take place selectively to the modified masking layer doped with boron, by means of a KOH etching.
A further method step provides that a buried plate is formed around the lower region of the trench, whereby dopant is brought into the substrate. This is possible for example by means of a gas phase doping with arsenic or phosphorus. The buried plate acts as an outer capacitor electrode of the trench capacitor, and may be electrically connected with other buried plates of adjacent trench capacitors via a buried layer, to form a common counter-electrode.
A further method step provides that a capacitor dielectric is formed in the lower region of the trench on the substrate and in the upper region of the trench on the insulating collar. The capacitor dielectric is used as an insulating layer between the two capacitor electrodes of the trench capacitor, which form the outer capacitor electrode of the buried plate. A further construction of the inventive method provides that the conductive trench filling is sunk up to the second sinking depth, and subsequently the capacitor dielectric is etched isotropically, whereby it is etched back up to the second sinking depth, and subsequently the insulating collar is etched isotropically, whereby this collar is etched back up to the second sinking depth, and subsequently the conductive trench filling is sunk in up to the third sinking depth, and subsequently the capacitor dielectric is isotropically etched, whereby it is etched back up to the third sinking depth.
The specified method steps form a structure wherein the conductive trench filling and the capacitor dielectric are sunk into the trench up to the third sinking depth, and the first insulating layer is sunk into the trench up to the second sinking depth. The second sinking depth is thereby situated between the first sinking depth and the substrate surface, and the third sinking depth is situated between the first sinking depth and the second sinking depth. This has the advantage that the subsequently grown selective epitaxy grows for example only on the side wall of the trench above the second sinking depth, which is situated at a distance from the third sinking depth, and thus from the filling height of the conductive trench filling.
A further method step provides that a contact layer is formed in the trench on the conductive trench filling. The contact layer has the advantage that it prevents an epitaxial growth on the contact layer, and thus on the conductive trench filling, in the subsequent selective epitaxy. Through this, for example a polycrystalline growth is avoided.
A further method step provides that an intermediate layer is formed on the selectively grown epitaxial layer. The intermediate layer has the advantage that the monocrystalline substrate and the epitaxially grown layer can be protected from crystal imperfections which could otherwise progress out of the trench into the substrate, and could result in damage to the selection transistor.
A further method step provides that a process step is carried out at a temperature between 900xc2x0 C. and 1050xc2x0 C. in an atmosphere containing hydrogen, at a pressure of approximately 20 Torr (2666 Pascal), whereby crystal defects are reduced in the epitaxially grown layer.
The process step can also be carried out at a temperature between 500xc2x0 C. and 900xc2x0 C., at a pressure of less than 10xe2x88x928 Torr, whereby the selective epitaxy is carried out in UHV (ultra-high vacuum).
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for manufacturing a trench capacitor of a memory cell of a semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.